A semiconductor integrated circuit (IC) has a large number of components, such as transistors, logic gates, and diodes that are fabricated by forming layers of different materials and different geometric shapes on various regions of a silicon wafer. The large number of components in the IC may be facilitated with an Electronic Design Automation (EDA) tool that allows a semiconductor designer to position and connect various shapes on the IC. The semiconductor designers create a custom design of such ICs, printed-circuit boards, and other electronic circuits containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated using EDA technologies that typically run on an operating system in conjunction with a microprocessor-based computer system or other programmable control system.
As part of the IC design, the collections of various shapes forming features or devices are inserted into the circuit design as cells. The EDA tools facilitate breaking a complex circuit design into small sub-designs that include the cells. These cells can be instantiated as instances inside other cells, thus enabling hierarchical design and re-use when the same cell is instantiated more than one time. The cells implement logic or other predefined functions using various integration technologies. Typically, programmable cells, also known as parameterized cells (pcells), have been used in designing circuits. The EDA tools facilitate generation of the pcells, which are a type of cell for which various parameters of their circuit components can be specified. The EDA tools may facilitate automatic generation of the pcells by the FDA tool based on the values of its parameters. The source code of the pcells is executed by the EDA tool that uses modified or default parameter values to generate a customized instance of the pcells. Also, the pcells are more flexible than a conventional cell because the different instances of the pcells may have different parameter values.
Conventional layout tools provide a customizable abutment process for the pcells. The abutment process provides the functionality to abut instances of the pcell views resulting in a chain of abutted instances which form a compact layout. In order to initiate abutment, the semiconductor designer overlaps a set of instances of the pcell with another set of instances of the pcell. The layout tool detects the overlap of abuttable instances and automatically runs a process design kit (PDK) defined abutment function associated with those overlapping pcells. Alternatively, the semiconductor designer selects a set of instances of the pcell that might not currently be overlapping and then invokes a specific layout editor command requesting that instances be abutted together to form an abutted chain. An abutment updating function then updates the instances parameters for the pcell and re-evaluates those parameters to create a new pcell sub-master that takes the abutment into account along with the overlap margin. The abutment updating function is provided as part of the PDK together with the pcells, and similar to the pcells, the abutment updating function is also written in an extension language.
In the conventional abutment tools, the tool will only abut a successive pair at one time until obtaining a chain of abutted instances. Because the abutment tool available today only abuts a pair of instances at any given point in time, there is no context of the full chain in which those instances actually reside or are changed. As the processes are becoming more advanced and with the increasingly complex design rules in todays advanced processes, the context of where the instances are within the chain as a whole is becoming more important. For example, simulation parameters are set based on where the instances are within the chain. In situation having a transistor instance of the pcell in the middle of the chain, then some of simulation parameters of the transistor instance depend on how far it is from a left end and a right end of the chain, and/or a top end of the chain and a bottom end of the chain.
In one exemplary scenario, there are four selected instances for abutment where the left most instance is called I1 followed by I2, I3, and I4. With a conventional abutment tool, the abutment tool will initially abut I1 and I2, and the abutment tool will assume that chain is going to be the final chain. Accordingly, the abutment tool will compute new parameters and geometries assuming that the final chain was created. Later, the third instance I3 is abutted into the chain (of I1 and I2) by the tool. At this time, the abutment tool traverses back along the created chain (of I1 and I2) and discovers that the assumptions made earlier on the created chain (of I1 and I2) are actually not correct. This will lead to deletion of the geometries and/or adjustment of the parameters for the back of the created chain (of I1 and I2). Similarly, when the final instance I4 is abutted, the abutment tool would again modify the parameter values as well as the geometries as the abutment tool will discover that I3 is now no longer the end of the created chain (of I1, I2, and I3).
Therefore, using the existing abutment tools, it is not possible to generate a correct layout at the time each pair of instances are abutted, because some features of the layout can only be created when more instances in the chain have been abutted, and all the instances in the chain are correctly positioned relative to each other. Further, the parameters of the instances in the chain for simulation can only be configured correctly when the chain is fully formed. Therefore, there is a need in the art for methods and systems that addresses the above mentioned drawbacks of conventional techniques employed in abutment of pcell instances.